A typical digital shift register (DSR) consists of a chain of D-type flip-flops, one for each bit, in which the Q output of each stage is connected to the D input of the following stage. When a clock signal is asserted, the flip-flops each hold a data value present on the D input on their Q outputs. The data value is held until the clock signal is asserted again, when the value on the Q output is replaced by whatever new data value is present on the D input. FIG. 1 illustrates an example of a typical digital shift register having N flip-flops 101.1 to 101.N. The flip-flop would typically have a static CMOS design which consumes minimal power during static operation, but consumes significant power when clocked due to internal transitions at each clock edge. Clocking Power consumption arises even when the data on the flip-flop's output does not change. Further, the shift register dissipates additional power due to the global clock buffer, which must charge and discharge the capacitance of the global clock bus 110.
The typical digital shift register may be used in a number of contexts for a number of applications. One example application may be a control signal for digital image processing. A digital image may comprise a matrix of N by M pixels, and an image capturing device may include a sensor array of N by M sensors. An example of this is described further below with regard to FIG. 3. In the example, the control signal may be used to scan the image or sensor array pixel by pixel (or sensor by sensor). In this context, the control signal may be a horizontal shift register, shifting a logical “1” on every clock cycle (or every N clock cycles in other contexts, such as the vertical shift register or vice versa). The sensor intersecting the active HSR flip-flop and VSR flip-flop may then be the one active sensor of the N by M array. In this application, the shift registers may each have only two flip-flops changing state values (e.g., the current active flip-flop going back to an inactive state, and the next flip-flop becoming active), while the remaining N−2 and M−2 flip-flops experience no state change. Despite the lack of a state change in these flip-flops, they still consume power on each clock pulse. Using as an example a high definition video frame of 1920 pixels by 1080 pixels, there are 3,000 flip-flops used to scan the 1920 by 1080 sensors, 99.87% of which consume power on each clock cycle without actually needing to change states.
Accordingly, there is a need in the art for a control mechanism for use in shift registers that conserves power that otherwise will be wasted when a flip-flop stage inputs data that has a same value as is already stored in the flip-flop.